Veredas Ramírez, Francisco Javier2024-05-202024-05-202017-07-07https://hdl.handle.net/20.500.14468/14540This Master's thesis investigates the critical path optimization in the FPGA's placement. An initial investigation of the FPGA's placement problem shows that the minimization of the traditional cost function used in the simulated annealing's placement not always produce a minimal critical path. Therefore, it is proposed to use the routing algorithm as a cost function to improve the nal critical path. The experimental results conrm that this new cost function has better quality results than the traditional cost function, at the expenses of longer execution time. A genetic algorithm using the routing algorithm as a cost function is found to reduce the execution time meanwhile is maintained a minimal critical path. The use of genetic algorithms with the new cost function will be useful in those cases where a minimum critical path is needed. Furthermore, this work investigates the use of genetic algorithm using the traditional cost function. In this case, no better critical path in comparison with a simulated annealing's placement is observed.enAtribución-NoComercial-SinDerivadas 4.0 Internacionalinfo:eu-repo/semantics/openAccesstesis de maestría