library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity MICRO is
port ( RS, CK : in std_logic;
Databus : inout std_logic_vector(15 downto 0);
Dirbus : out std_logic_vector(11 downto 0);
R_W, DIRV, DATV : out std_logic );
end MICRO;
architecture PROCESADOR of MICRO is
-- acumuladores, resultado e indicadores
signal A, B : std_logic_vector(15 downto 0);
signal R : std_logic_vector(15 downto 0);
signal N, C, V : std_logic;
signal Nulo, Carry, V_over : std_logic;
-- registros de la parte de control
signal RI : std_logic_vector(15 downto 0);
signal PC : std_logic_vector(11 downto 0);
signal CC : std_logic;
-- partes de la instrucción
signal COD : std_logic_vector(3 downto 0);
signal DIR : std_logic_vector(11 downto 0);
-- señal de validación de dato
signal DATVint : std_logic;
-- ALU como componente
component ALU port( A, B : in std_logic_vector(15 downto 0);
COD : in std_logic_vector(3 downto 0);
CC : in std_logic;
R : out std_logic_vector(15 downto 0);
C : in std_logic;
Nulo, Carry, V_over : out std_logic );
end component;
begin
-- partes de una instrucción
COD <= RI(15 downto 12); DIR <= RI(11 downto 0);
-- inserción de la ALU como componente
U1: ALU port map( A => A, B => B, COD => COD, CC => CC, R => R,
C => C, Nulo => Nulo, Carry => Carry, V_over => V_over );