(ExpressProject "ADC" (Folder "Design Resources" (Folder "Library")) (Folder "Simulation Resources" (DefaultFolder "In Design") (UserName "Standard") (LastModified "Thu May 04 22:30:21 2006") (Folder "In Design" (File ".\circuito.vhd" (Type "VHDL Netlist")) (File ".\estimulo.vhd" (Type "VHDL Netlist")) (Document 5 ".\circuito.vhd" (Window "44 2 2 480 382 -4 -23 66 730 66 336")) (Document 5 ".\estimulo.vhd" (Window "44 0 1 -1 -1 -4 -23 132 796 132 402")) (Document 0 (Signal "estimulos" "Ve" 4 0) (Signal "estimulos" "B" 4 0) (Window "44 2 2 160 378 -4 -23 88 756 88 362")) (Document 1 (Signal "estimulos" "Ve" 4 0) (Signal "estimulos" "B" 4 0) (Signal "estimulos" "B[3]" 4 1) (Signal "estimulos" "B[2]" 4 1) (Signal "estimulos" "B[1]" 4 1) (Signal "estimulos" "B[0]" 4 1) (Window "44 2 2 320 378 -6 -25 110 778 110 384")) (Options (AssertBeep 1) (AssertLog 1) (AssertMsg 1) (AssertStop 1) (BreakBeep 1) (BreakLog 1) (BreakMessage 1) (BreakStop 1) (DisableLoopChecking 1) (FileOpen "C:\Mis documentos\VHDL\Puertas lógicas\Capítulo8\ADC 0805\VHDL") (InstructionStep 1) (InteractiveUpdate 1) (ITCEnabled 1) (ListDisplayTop 1) (LogTimeStamp 1) (MiscOptLastPage 0) (PlaAddToProject 1) (PlaClockToOutput 0) (PlaCombinational 0) (PlaResolution -1) (PlaSetupTime 0) (PlaSpeedGrade 15) (PlaTriStateEnable 0) (Radix 0) (RunResolution 4) (RunTime 12000) (SDFTiming 1) (TimeCursorSnap 0) (TimingBeep 0) (TimingLog 1) (TimingMsg 0) (TimingStop 0) (VHDLStandard 1) (WaveDisplayTop 1))) (Folder "Timed")) (Folder "Outputs") (Folder "Referenced Projects"))