(ExpressProject "PP_4-18_VHDL" (Folder "Design Resources" (Folder "Library")) (Folder "Simulation Resources" (DefaultFolder "In Design") (UserName "Javi") (LastModified "Wed Mar 22 23:07:27 2006") (Folder "In Design" (File ".\pp_4-18_vhdl.vhd" (Type "VHDL Netlist")) (File ".\pp_4-18_stim.vhd" (Type "VHDL Netlist")) (Document 5 ".\pp_4-18_vhdl.vhd" (Window "44 0 1 -1 -1 -4 -30 119 1197 204 789")) (Document 5 ".\pp_4-18_stim.vhd" (Window "44 0 1 -1 -1 -1 -1 66 1144 87 672")) (Document 0 ".\pp_4-18_wave" (Signal "estimulos" "a0" 4 0) (Signal "estimulos" "a1" 4 0) (Signal "estimulos" "a2" 4 0) (Signal "estimulos" "a3" 4 0) (Signal "estimulos" "a4" 4 0) (Signal "estimulos" "a5" 4 0) (Signal "estimulos" "a6" 4 0) (Signal "estimulos" "a7" 4 0) (Signal "estimulos" "I" 4 0) (Window "44 0 1 -1 -1 -1 -1 92 1170 14 599")) (Document 1 ".\pp_4-18_list" (Signal "estimulos" "a0" 4 0) (Signal "estimulos" "a1" 4 0) (Signal "estimulos" "a2" 4 0) (Signal "estimulos" "a3" 4 0) (Signal "estimulos" "a4" 4 0) (Signal "estimulos" "a5" 4 0) (Signal "estimulos" "a6" 4 0) (Signal "estimulos" "a7" 4 0) (Signal "estimulos" "I" 4 0) (Window "44 0 1 -1 -1 -1 -1 107 1185 357 942")) (Options (AssertBeep 1) (AssertLog 1) (AssertMsg 1) (AssertStop 1) (BreakBeep 1) (BreakLog 1) (BreakMessage 1) (BreakStop 1) (DisableLoopChecking 0) (FileOpen "D:\UNED\E. Digital\TRABAJO\OrCAD\CAPITULO 4\PROPUESTOS\PP4-15\VHDL") (InstructionStep 1) (InteractiveUpdate 1) (ITCEnabled 1) (ListDisplayTop 1) (LogTimeStamp 1) (MiscOptLastPage 0) (PlaAddToProject 1) (PlaClockToOutput 0) (PlaCombinational 0) (PlaResolution -1) (PlaSetupTime 0) (PlaSpeedGrade 15) (PlaTriStateEnable 0) (Radix 0) (RunResolution 3) (RunTime 2000) (SDFTiming 1) (TimeCursorSnap 0) (TimingBeep 0) (TimingLog 1) (TimingMsg 0) (TimingStop 0) (VHDLStandard 1) (WaveDisplayTop 1))) (Folder "Timed")) (Folder "Outputs") (Folder "Referenced Projects"))